제조과정을 고려하지 않은 PCB 설계시 문제점

 

아래 링크가 정말 자세히 나와있다. 참고하면 좋다. (reference: link below)

www.raypcb.com/common-pcb-design-mistakes/

Common PCB Design Mistakes – Printed Circuit Board Manufacturing & PCB Assembly – RayMing

짧게 읽기쉽게 요약했으므로 자세한 사항은 영문을 참고.

 

(요약)

Design Rule Checker (DRC):

The purpose of the DRC is to cross check the PCB layout design against the capabilities/constraints of PCB fabrication shop. These constraints are communicated in terms of maximum tolerances to the PCB layout design engineer and the design engineer simply input these values to the DRC checker and Run DRC. As a result, any discrepancy is identified and rectified. The common constraints that DRC run can check are trace width, hole to trace clearance, overlaps, drill size, keep out, angle, blind via ratio and many others.

 

PCB제조업체의 허용치(제작 가능한가?)에 대한 Rule. 제조업체는 설계자에게 Rule을 전달하고, 설계자는 해당 Rule에 맞춰 설계를 진행해야 함. 모든 DRC조건이 만족할 때 비로소 설계데이터가 제조 가능. 일반적인 DRC 검사는 Trace 폭, 간격, 겹침, 드릴홀 크기, Keep out(이격거리), 각도, blind via 비율 등

 

 

Design For Manufacturing (DFM):

On the other hand, Design for Manufacturing (DFM) is a tool that can cover the grey areas that are left (remain unidentified) by DRC. This DFM (unlike DRC which is not an Ad-on but an integrated tool of CAD software) is an Ad-on provided for additional cost as an extra service by PCB fabricators to the customer. This can ultimately raise the cost of PCB because of DFM dedicated software is expensive and require manpower training. The DFM check will result in more qualified, reliable and high yield end product PCB.

 

DFM은 제조적인 관점에서 DRC체크로도 식별할 수 없는 영역을 탐지. 보통 add-on 툴로써 설계툴의 옵션으로 붙음.

일반적인 PCB설계보다 더 복잡한 정밀한 PCB설계를 위해 PCB제조업체가 추가적으로주는 디테일한 Rule.

 

 

 

1. Starved thermal pads

It is commonly observed that when reworking on a PCB during de-soldering the component from PCB, it takes lot of time, heat and effort. This is because the copper is a good conductor of heat. So when applying heat from soldering iron, the heat is wasted through the copper pour into the copper plane because the pad is completely surrounded by copper. So the component pad does not get enough heat to melt the solder and remove the electronic component.

 

This issue is resolved by soldering the component on thermal pad. Thermal pad can have 2 or 4 thermal relief traces that connect the pad to the copper pour to copper plane.  The air gap reduces the contact area so heat is not dissipated/wasted.

 

Now the design issue occurs when the thermal relief traces is not properly connected to copper pour or plane. The reason is the close proximity of multiple vias / pads or small spacing in between vias / pads. These small space may be cleared by DRC checker, but in actual the thermal relief traces will disturb the effected via and can displace vias from its copper pour.

납땜할 때 납의 녹는점을 유지하기 위한 온도가 중요, thermal relief 를 통해 열이 방출되는 시간을 조절할 수 있다. thermal relief trace가 얇으면 높은 온도가 오래 유지될 수 있고, 두껍다면 금방 열이 plane으로 방출되어 녹는점의 온도를 오래 유지하기 힘들다. 따라서 납땜이 잘되기 위한 적당한 두께를 지니도록 한다.

 

보통의 thermal pad는 airgap(흰색)을 두고 해당 pad와 copper plane간의 이격거리를 두어 급격한 열의 발산이 일어나지 않도록 도와준다.

 

 

2. Acid Traps Acute Angle

 

During the PCB design process, the design engineer can unknowingly makes a mistake. This mistake is that the two traces meet/cross each other at “acute angles” i.e less than 90 . As a result, the corners are made in the trace crossing point that can “trap” acid inside it. The acid referred here is the PCB etching solution used to etch away unwanted/excess copper from the PCB and only useful copper is left for making tracks/traces. This acid / etching solution is commonly available Ferric Chloride or Hydrochloric Acid.

 

The “acid trap hole” is another similar thing that arises due to very less gap between the trace and via. This will cause the space or pockets to form and retain the acid inside.

 

These acid if trapped for long time, can eat away copper trace and hence creates open circuit that can render the PCB board defective. The possibility of acid traps in multilayer PCB is very high. Recent advancement in etching method (photo activated etching solution) of PCB has made this issue trivial but still best practice must be ensure to avoid acute angle traces.

(아래 참고)

ansan-survivor.tistory.com/629

PCB에서 acid trap 이란? (PCB 제조에서 발생하는 문제)

 

3. Copper Pour with Narrow Trace:

In some cases, like SOIC-08 IC package, the pad pitch is 5 mil and let’s suppose the fabrication min spec is 10mil so it can short copper pour and pad as shown in the figure. In this figure the upper pour diagram shows the copper pour has width 0.005 inch while lower pour is 0.016 inch. And you can see that the lower pour is not present between the pads of SOIC. In Eagle Software this can be done by changing the copper pour width. This is the good practice as shown in lower pour and upper pour shown is a mistake that a PCB designer can make

 

If this mistake is made, this can result in breakage of this very thin 5 mil trace in little pieces which can float in other components of PCB to create short circuit.

Pad의 Pitch(pad간 중심거리)가 5mil이고 제조업체의 사양이 10mil일 때, 위 그림의 윗부분의 pad사이에 있는 Copper pour에는 단락이 일어날 것이다. 이러한 실수가 발생하면 얇은 5mil 파편이 돌아다니면서 문제를 일으킬 수 있다. 

즉, 제조업체의 최소 제작 사양을 확인하고 제작

 

 

 

 

4. Inadequate annular ring size

The layers of PCB are interconnected by means of vias. The vias are made by drilling the holes on both sides and then plating the walls of holes thus interconnecting the inner layers and two external layers (sides) of PCB.

 

Now if the pad size is very small then the holes bored will take the large space on pad leaving very narrow or inadequate ring size. This is called annular ring. This insufficient annular ring is caused by inaccuracy in drill bit position and inaccuracy in hitting the target to drill holes .

Pad의 크기가 매우작은 경우 drill hole이 차지하는 사이즈가 크게될 것인데, 이는 pad의 두께가 얇게 되어 올바른 Land Ring을 형성하기 힘듦.  그렇게 되면 Drill bit가 Hole을 뚦을때 살짝만 어긋나도 위와 같이 치우처진 via가 생성될 수 있음 (부적합한 갈고리 모양 via = annular ring)

적절한 Pad크기와 Hole의 크기를 지정해야 함)

 

 

 

5. Via in Pads

Sometimes it is important for PCB designer to place a via in Pad of a component. This is done for sake of compact PCB routing. In traditional routing, DRC error can raise due to drill size and trace width etc. So for small pitch components like sub 0.5mm it is inevitable to use a via in Pad as shown in figure.

However the drawback of this is that this via will work as a straw that will suck the solder away from the pad and will cause the inadequate soldering of component upon the pad. The solution to this problem is to use “Capped Via” as shown in this figure. Filling the conductive epoxy is also good.

전통적인 via생성 방식은 pad로 부터 튀어나와 via를 만들지만, 요즘처럼 부품의 크기가 작아져 pitch가 작아지는 경우에는 via를 pad위에 뚫는게 필수가 되고 있다. (위 그림처럼 "via in pad")

그러나 저런 경우 부품 납땜시 via hole을 통해 납을 흡수해버려 납땜이 잘 안된다. 그래서 저런 부분에는 Conductive epoxy소재로 가득채워 "Capped and Plated Via"를 만들어 사용한다.

 

 

6. Copper Layer near the board edge

The copper can be brought just close to the edge of PCB board because the design engineer does not include the “keep out layer” or “outline layer” in the Gerber Files. This keep out layer is very important because if it is not included then the copper can be exposed  to air and can cause trouble when boards are panelized resulting in short circuiting the copper layers. This feature can be easily caught in both DRC and DFM.

설계 엔지니어가 설계시 Board에 끝부분(outline)으로부터 이격거리(Keep out layer)를 설정하지 않는다면 Copper plane은 보드의 맨 끝부분(edge)까지 채워져 있을 것이다. 그런데 나중에 Panlize(여러 PCB보드를 자르는 것)을 하게되면 해당 Copper plane이 공기에 노출되는 문제가 있고, 또 Panlizing 과정중에 Short가 발생할 수도 있다.

따라서 설계시 Keep out layer 를 잘 지정하자 (DRC나 DFM 기능을 적절히 활용)

 

 

7. Missing solder mask between pads

Solder mask is also called solder resist. It is used to protect the solder away from the copper track that you do not want to solder. For example in very small pitch components like QFN package 0.4mm pitch it is nearly impossible to apply solder mask in this tight space so it is common that you will not find solder mask because of standard DRC rules. This will result in a problem of solder bridge as shown in figure.

납의 흐름을 방지시켜주는 soldermask(=solder resist)를 잘 적용해야 한다. QFN 패키지 같은 매우적은 pin간의 pitch(0.4mm)지닌 pad사이에서 솔더마스크가 없다면 Solder-Bridge(위 사진처럼 납땜하다 서로 연결되는)가 발생할 수 있다. 이점을 주의 한다.

 

 

 

8. Tombstoning

During the PCB assembly, when the small SMT passive components being soldered, the Tombstoning is caused by the improper wetting. When the solder paste starts to melt, an imbalanced torque at the ends of the component terminals causes the component to lift from one end.  The component will be lifted from the end where the paste is wet. This Tombstoning can damage the PCB yields and raise cost of production. Other factors that cause Tombstoning are

1- Improper design of solder pads

2- Uneven solder paste printing

3- Uneven temperature of reflow oven

4- Placement of component parallel to reflow oven conveyer

매우 작은 SMD수동소자를 납땜할 때 위 사진처럼 Tombstoning(한쪽으로 세워짐)이 발생할 수 있다. 이는 양단을 붙잡고 있는 납이 동일하게 녹아 동일한 힘으로 소자를 붙잡아야 하는데, 불균형한 토크(힘)으로 인해 한쪽에서만 붙잡고 들어 올린다.

이 원인으로는 아래 와 같다.

1. 양단의 Solder pad Design의 문제 (한쪽은 얇고 한쪽은 두껍고) -> 두꺼운 쪽으로 힘을 더 받고 기울게 된다.

2. 양단에 고르게 분배되지 않은 soldring paste 문제

3. reflow oven 내에서 고르지 못한 온도

4. reflow oven 내에서 부품이 삐뚤게 배치되어 있을 때